In conventional photolithographic processing, integrated circuits are manufactured by exposing a pattern of features that are contained on a mask or reticle onto a wafer. Light passing through the transparent portions of the mask activates light sensitive resist materials on the wafer that are then chemically and mechanically processed to create the circuit features. The process continues building up the integrated circuit, layer by layer.
As circuit features become increasingly small and more densely packed, optical and other process distortions occur such that the pattern of features on the mask does not correspond to how the features will print on the wafer. Therefore, numerous resolution enhancement techniques (RETs) have been developed to improve the ability of the mask to print a desired pattern on the wafer. One resolution enhancement technique is optical and process correction (OPC). OPC operates by changing the mask pattern to precompensate for expected optical and process distortions such that a pattern of features printed on a wafer will match a desired target layout pattern. Another resolution enhancement technique is the use of subresolution assist features (SRAFs). Such features are small features placed on a mask or reticle that are too small to print on a wafer but operate to improve how an adjacent mask feature prints.
Another technique for improving the ability of a mask to print a desired pattern of features on a wafer is referred to as mask inversion. With mask inversion, a mathematical calculation is performed to determine what an optimal mask pattern should look like in order to create a desired pattern on a wafer. One mask inversion technique is described in published U.S. patent application Ser. No. 11/364,802 by Yuri Granik and assigned to Mentor Graphics Corporation of Wilsonville, Oreg., the assignee of the present invention, and is herein incorporated by reference. While inverse techniques can accurately determine the ideal mask pattern required to print a target pattern of features on a wafer, the methods can be computationally intensive.
Given these problems, there is need for a technique of improving the ability of a mask to print a desired pattern of features on a wafer that approaches the accuracy of a mask inversion technique but is faster to compute and easier to manufacture.